1. Field of the Invention
The invention relates to the technical field of multilayer printed circuit board (PCB) and, more particularly, to a low noise multilayer PCB.
2. Description of Related Art
Power bus noise caused by the switching of integrated circuits (ICs) such as clock generators or power amplifiers is a significant source of electromagnetic interference (EMI). It may propagate to the other components on the PCB through parallel-plate structure formed by power and ground layer of the PCB. Typically, an isolation method is used to avoid sensitive analog ICs (such as an analog to digital converter) from being influenced by the noise. Namely, some slots are cut on the power and ground metal layers to separate the noise sources into a certain area of the PCB and isolate the noises from being delivered easily to the other circuits.
FIG. 1(A) shows the metal layers of a typical four-layer PCB. As shown in FIG. 1(A), two metal layers, power layer 130 and ground layer 120, provide a source and a return current path for the circuit on the PCB, respectively. In addition, the PCB has two signal layers 110 and 140 which provide metal connections of different electronic components on the PCB.
FIG. 1(B) is a cross-sectional view of FIG. 1(A). As shown in FIG. 1(B), the dielectric layer 150 on the PCB is divided into three parts by the metal layers. FIG. 1(C) shows the area where the power bus noise exits. Because of the parallel-plate structure formed by the upper and lower metal layers 120 and 130, the region II benefits the electromagnetic propagation.
FIG. 2(A) is a top view of using an isolation method to separate a PCB into two areas in accordance with the prior art. Slots are cut on the power and ground metal layers with identical pattern. Although the isolation effect of this method is quite well, it would make the power layer to be discontinuous and degrade the signal integrity of the signal lines across the gaps.
Typically, the circuit components are placed on the top side of the PCB and use the signal layer 110 to route the signal trace as shown in FIG. 1(D). In the circuit theory, the complete current path must form a closed loop. Typically, the return current of the signal trace is flowing on its adjacent layer either the ground layer 120 or the power layer 130. Therefore, if the ground layer 120 or power layer 130 is separated by one or more gaps, the signal integrity of signal traces across the gaps may become worse.
To improve the signal integrity, a metal neckline for each of the power layer and ground layer are provided at the location where the signal lines pass through the gap, as shown in FIG. 2(B). For the convenience in the design process, the power layer and the ground layer usually use the same pattern. Namely, the location of the gaps and the metal connections on the power layer and the ground layer are the same.
However, there still exist some disadvantages for such a metal connection. For example, the effect of the isolation will become worse in some frequencies, and become even worse for the increased width of a metal connection.
The previous study shows that using a narrow metal connection on each of the power layer and ground layer can improve the isolation effect, but the signal lines on the adjacent layer are difficult to be routed within the metal connection region. Conversely, using a wider metal connection will make routing of the signal lines to be easy, but the isolation will become worse. Therefore, there is a conflict between the width of the metal connection and the isolation effect in the prior art. There is a need to provide an improved power layer and ground layer structure of the multilayer PCB.